1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the invention relates to a latch circuit and a flip-flop circuit which are data holding circuits using MOS transistors. The present invention also relates to a buffer circuit for use to input a signal to the data holding circuits.
2. Description of the Background Art
FIG. 24 is a circuit diagram of a conventional latch circuit. The latch circuit is shown as comprising transmission gates TG1 to TG4, inverter gates INV1 and INV2, first and second data input terminals DI and DIB, first and second clock input terminals CK and CKB, and first and second data output terminals DO and DOB.
The elements constituting the latch circuit will be described below. Each of the transmission gates TG1 to TG4 includes a PMOS transistor and an NMOS transistor which are connected in parallel and which have commonly connected source electrodes and commonly connected drain electrodes to form two current electrodes. Gate electrodes of the PMOS transistors of the transmission gates TG1 and TG2, and gate electrodes of the NMOS transistors of the transmission gates TG3 and TG4 are commonly connected to the first clock input terminal CK. Gate electrodes of the NMOS transistors of the transmission gates TG1 and TG2, and gate electrodes of the PMOS transistors of the transmission gates TG3 and TG4 are commonly connected to the second clock input terminal CKB.
The first data input terminal DI is connected to a first current electrode of the transmission gate TG1. A second current electrode of the transmission gate TG1 is connected to an input terminal of the inverter gate INV2 and is also connected to an output terminal of the inverter gate INVL through the transmission gate TG3.
Likewise, the second data input terminal DIB is connected to a first current electrode of the transmission gate TG2. A second current electrode of the transmission gate TG2 is connected to an input terminal of the inverter gate INV1 and is also connected to an output terminal of the inverter gate INV2 through the transmission gate TG4. The output terminals of the inverter gates INV1 and INV2 are connected to the first and second data output terminals DO and DOB, respectively.
Signals to be inputted to the latch circuit are described below. A signal at H level (high level, voltage level of a first power supply VDD) and a signal at L level (low level, voltage level of a second power supply GND) are mutually exclusively applied to the first data input terminal DI and the second data input terminal DIB. The signals at H and L levels different from each other are those at voltage levels indicative of opposite binary logics.
A data combination wherein data signals to be applied to the first and second data input terminals DI and DIB are at H and L levels respectively is referred to as first data DATA1. Similarly, a data combination wherein the data signals to be applied to the first and second data input terminals DI and DIB are at L and H levels respectively is referred to as second data DATA2.
Likewise, a signal at H level and a signal at L level are mutually exclusively applied to the first and second clock input terminals CK and CKB.
A data combination wherein clock signals to be applied to the first and second clock input terminals CK and CKB are at H and L levels respectively is referred to as a first clock input state CLK1. Similarly, a data combination wherein the clock signals to be applied to the first and second clock input terminals CK and CKB are at L and H levels respectively is referred to as a second clock input state CLK2.
The latch circuit has the above described connection and arrangement. Thus, the transmission gates TG1 and TG2 form a pair, and the transmission gates TG3 and TG4 form a pair. The two pairs are mutually exclusively in and out of conduction.
A series of circuit operations of the latch circuit are discussed below. Signal setting for determining the circuit operations (1) to (4) of the latch circuit will be described below. Signal setting numbers correspond respectively to circuit operation numbers.
Signal setting (1)
The latch circuit is in the first clock input state CLK1, and receives the first data DATA1.
Signal setting (2)
The latch circuit is in the second clock input state CLK2, and receives the first data DATA1.
Signal setting (3)
The latch circuit is in the first clock input state CLK1, and receives the second data DATA2.
Signal setting (4)
The latch circuit is in the second clock input state CLK2, and receives the second data DATA2.
FIGS. 25A to 25C are waveform charts representing a timing chart of the circuit operations (1) to (4) of the latch circuit in response to the signal settings (1) to (4). FIG. 25A shows the signal levels at the first and second data input terminals DI and DIB, FIG. 25B shows the signal levels at the first and second clock input terminals CK and CKB, and FIG. 25C shows the signal levels at the first and second data output terminals DO and DOB. The latch circuit functions to receive the data signals at the first and second data input terminals DI and DIB in synchronism with the clock signals to output the data signals which are phase-shifted by a half cycle of the clock signals, as will be described below with reference to FIGS. 25A to 25C.
1. Circuit operation (1) of latch circuit
The transmission gates TG1 and TG2 are off whereas the transmission gates TG3 and TG4 are on. Thus, the signals at the H and L levels applied respectively to the first and second data input terminals DI and DIB are not provided to the interior of the latch circuit.
2. Circuit operation (2) of latch circuit
The transmission gates TG1 and TG2 are on whereas the transmission gates TG3 and TG4 are off.
The signal at H level applied to the first data input terminal DI is applied to the inverter gate INV2 through the transmission gate TG1. In response to this signal, the inverter gate INV2 outputs a signal at L level through the second data output terminal DOB. Likewise, the inverter gate INV1 receives the signal at L level at the second data input terminal DIB through the transmission gate TG2 to output a signal at H level through the first data output terminal DO. Therefore, the first and second data output terminals DO and DOB output the first data DATA1.
3. Circuit operation (3) of latch circuit
The transmission gates TG1 and TG2 are off whereas the transmission gates TG3 and TG4 are on. Thus, the first and second data input terminals DI and DIB and the input terminals of the inverter gates INV2 and INV1 are isolated from each other by the transmission gates TG1 and TG2 which are off, respectively. Specifically, although the data DATA2 are applied to the first and second data input terminals DI and DIB, the signals at L and H levels are continuously applied to the input terminals of the inverter gates INV1 and INV2 respectively in a loop formed by the inverter gates INV1, INV2 and the transmission gates TG3, TG4 which are on. Therefore, the first data DATA1 are outputted continuously.
4. Circuit operation (4) of latch circuit
The transmission gates TG1 and TG2 are on, and the inverter gates INV1 and INV2 are electrically connected to the second and first data input terminals DIB and DI, respectively. The inverter gates INV1 and INV2 receive the signals at H and L levels to output signals at L and H levels through the first and second data output terminals DO and DOB, respectively. Therefore, the first and second data output terminals DO and DOB output the second data DATA2.
Subsequently, the first and second clock states CLK1 and CLK2 are alternately repeated in similar manner, and third data DATA3 phase-shifted by a half clock cycle are transmitted through the latch circuit.
A conventional flip-flop circuit will be described below which is provided by connecting two latch circuits shown in FIG. 24. FIG. 26) is a circuit diagram of a flip-flop circuit disclosed in "IEICE TRANSACTIONS on Electronics, vol. E78-C, No. 12, Dec. 1995, pp.1746-1753".
The flip-flop circuit of FIG. 26 comprises transmission gates TG1 to TG8, inverter gates INV1 to INV4, first and second data input terminals DI and DIB, first and second clock input terminals CK and CKB, and first and second data output terminals DO and DOB.
A process for connecting two latch circuits together is discussed below. As illustrated in FIG. 26, a first latch circuit comprises the transmission gates TG1 to TG4 and the inverter gates INV1 and INV2, and has the same connections of the elements as the latch circuit of FIG. 24. A second latch circuit comprises the transmission gates TG5 to TG8 and the inverter gates INV3 and INV4 which are connected in corresponding relation to the transmission gates TG1 to TG4 and the inverter gates INV1 and INV2, respectively.
The first and second data output terminals of the first latch circuit are connected to the first and second data input terminals of the second latch circuit, respectively. The first and second data input terminals DI and DIB of the first latch circuit serve as the first and second data input terminals DI and DIB of the flip-flop circuit, respectively.
Similarly, the first and second data output terminals DO and DOB of the second latch circuit serve as the first and second data output terminals DO and DOB of the flip-flop circuit, respectively.
The first clock input terminal of the first latch circuit and the second clock input terminal of the second latch circuit are commonly connected to serve as the first clock input terminal CK of the flip-flop circuit. The second clock input terminal of the first latch circuit and the first clock input terminal of the second latch circuit are commonly connected to serve as the second clock input terminal CKB of the flip-flop circuit.
The flip-flop circuit is constructed as above described. Thus, the transmission gates TG1, TG2, TG7, TG8 simultaneously turn on and off, and the transmission gates TG3 to TG6 simultaneously turn on and off in exclusive relation to the transmission gates TG1, TG2, TG7, TG8.
The operation of the flip-flop circuit will be described on the basis of the above-mentioned signal settings (1) to (4). FIGS. 27A to 27C are waveform charts representing a timing chart of the flip-flop circuit and illustrate the same signals as those of FIGS. 25A to 25C.
The clock input states and corresponding data input states in the latch circuit are identical for each signal setting with those in the flip-flop circuit. Thus, the circuit operation of the first latch circuit is identical with that of the above described latch circuit. Accordingly, the second latch circuit and the flip-flop circuit including the first and second latch circuits are mainly described below, with the description of unnecessary portions of the first latch circuit dispensed with.
1. Circuit operation (1) of flip-flop circuit: Signal setting (1)
The transmission gates TG1, TG2, TG7, TG8 are off whereas the transmission gates TG3 to TG6 are on. Since the transmission gates TG1 and TG2 are off, the signals at the first and second data input terminals DI and DIB are not transmitted to the second latch circuit.
2. Circuit operation (2) of flip-flop circuit: Signal setting (2)
The transmission gates TG1, TG2, TG7, TG8 are on whereas the transmission gates TG3 to TG6 are off.
The signal at H level applied to the first data input terminal DI is fed to the inverter gate INV2 through the transmission gate TG1. In response to this signal, the inverter gate INV2 outputs a signal at L level to the second latch circuit. However, since the transmission gate TG6 is off, the output signal from the inverter gate INV2 is not applied to the input terminal of the inverter gate INV3.
Similarly, the inverter gate INV1 receives the signal at L, level at the second data input terminal DIB through the transmission gate TG2 to output a signal at H level. However, since the transmission gate TG5 is off, the output signal from the inverter gate INV1 is not applied to the inverter gate INV4.
3. Circuit operation (3) of flip-flop circuit: Signal setting (3) The transmission gates TG1, TG2, TG7, TG8 are off whereas the transmission gates TG3 to TG6 are on. Specifically, the second latch circuit is in the state of the circuit operation (2) of the latch circuit. The transmission gates TG5 and TG6 are on to permit the signals at H and L levels from the inverter gates INV1 and INV2 to be applied to the inverter gates INV4 and INV3, respectively. Thus, the first and second data output terminals DO and DOB output the first data DATA1.
In the latch circuit, the first and second data output terminals DO and DOB thereof output the first data DATA1 in the circuit operation (2) of the latch circuit. It is hence appreciated that the output from the flip-flop circuit further lags by a half clock cycle behind the output from the latch circuit.
4. Circuit operation (4) of flip-flop circuit: Signal setting (4)
The transmission gates TG1, TG2, TG7, TG8 are on whereas the transmission gates TG3 to TG6 are off. The second latch circuit is in the state of the circuit operation (3) of latch circuit.
In the second latch circuit, the transmission gates TG5 and TG6 are off and the transmission gates TG7 and TG8 are on. Thus, the output terminals of the inverter gates INV2 and INV1 are isolated from the input terminals of the inverter gates INV3 and INV4 by the transmission gates TG6 and TG5, respectively.
The inverter gates INV3 and INV4 and the transmission gates TG7 and TG8 which are on form a loop wherein the signals at L and H levels are continuously applied to the input terminals of the inverter gates INV3 and INV4, respectively. Thus, the first and second data output terminals DO and DOB continuously output the first data DATA1.
Subsequently, the first and second clock states CLK1 and CLK2 arc alternately repeated in similar manner, and the third data DATA3 phase-shifted by one clock cycle are transmitted through the flip-flop circuit. It will be understood from the comparison between FIGS. 27C and 25C that the flip-flop circuit functions to receive the data signals at the data input terminals in synchronism with the clock signals, to temporarily hold the data signals, and to output the data signals phase-shifted by 2 operations of the latch circuit.
In other words, the flip-flop circuit and the latch circuit have the same function of receiving the data signal in synchronism with the clock signal and outputting the phase-shifted data signal. However, a phase difference of one operation of the latch circuit exists between the flip-flop circuit and the latch circuit.
FIG. 28 illustrates a buffer circuit for applying a clock signal or a data signal to the flip-flop circuit or the latch circuit. The buffer circuit is shown as comprising a signal input terminal CIN, an inverter gate INV5 having an input terminal connected to the signal input terminal CIN, a first signal output terminal CKO connected to an output terminal of the inverter gate INV5 through an inverter gate INV6, and a second signal output terminal CKOB connected to the output terminal of the inverter gate INV5.
The circuit operation of the buffer circuit is described below. When a signal at H level is applied to the signal input terminal CIN, the first signal output terminal CKO outputs a signal at H level through the two inverter gates INV5 and INV6, and the second signal output terminal CKOB outputs a signal at L level through the one inverter gate INV5. Likewise, when a signal at L level is applied to the signal input terminal CIN, the first signal output terminal CKO outputs a signal at L level, and the second signal output terminal CKOB outputs a signal at H level. In this manner, the buffer circuit produces two signals which are logically opposite with each other in response to the input signal.
In the above described flip-flop circuit or the latch circuit, signals are applied through the buffer circuit to the first and second data input terminals DI and DIB or the first and second clock input terminals CK and CKB. To use the buffer circuit for the flip-flop circuit as a clock buffer circuit for a clock signal, four PMOS transistors and four NMOS transistors are connected to the output terminals of the clock buffer circuit, respectively. To use the buffer circuit for the latch circuit as the clock buffer circuit for the clock signal, two PMOS transistors and two NMOS transistors are connected to the output terminals of the clock buffer circuit, respectively.
FIGS. 29A to 29C are waveform charts representing a timing chart of the buffer circuit, and illustrate signal levels at the signal input terminal CIN, the second signal output terminal CKOB, and the first signal output terminal CKO, respectively. A switching delay d5 of the inverter gate INV5 and a switching delay d6 of the inverter gate INV6 are shown in FIGS. 29B and 29C.
As depicted in FIGS. 29A to 29C, after the input signal was applied to the signal input terminal CIN, the second signal output terminal CKOB provides the output signal with the switching delay d5 and the first signal output terminal CKO provides the output signal with a switching delay d5+d6.
As above stated, the conventional latch circuit includes the four PMOS and NMOS transistor pairs constituting the respective transmission gates. Similarly, the conventional flip-flop circuit includes the eight PMOS and NMOS transistor pairs constituting the respective transmission gates.
Such arrangements are disadvantageous because of increased areas of the conventional latch and flip-flop circuits.
When the clock buffer circuit is connected to the flip-flop circuit, the four PMOS transistors and four NMOS transistors are connected to the first and second signal output terminals CKO and CKOB of the clock buffer circuit, respectively. When the clock buffer circuit is connected to the latch circuit, the two PMOS transistors and two NMOS transistors are connected to the first and second signal output terminals CKO and CKOB of the clock buffer circuit, respectively.
This excessively increases the load capacitance of the output terminals of the clock buffer circuit, causing the clock buffer circuit to consume a large amount of power during charging and discharging of the load capacitance.
Further, the conventional buffer circuit, wherein the number of inverter gates connected between the signal input terminal CIN and the first signal output terminal CKO is different from the number of inverter gates connected between the signal input terminal CIN and the second signal output terminal CKOB, causes a time delay between the signals outputted from the first and second signal output terminals CKO and CKOB. Additionally, two inverter gates between the first signal output terminal CKO and the signal input terminal CIN have a delay causing a corresponding signal output delay, resulting in low operating speed of the flip-flop circuit or latch circuit.